Design and Implementation of a Time-to-First-Spike Based Spiking Neural Network Using Digital CIM Architecture and SOLIF Neurons

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Published: Sep 29, 2026
DOI: https://doi.org/10.66669/cineforum.v66iS7.1684
Keywords:
spiking neural network, time-to-first-spike, computing in memory, SOLIF neuron, digital-to-spike converter, winner-take-all, Verilog, neuromorphic hardware

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Swetha Chukka
D. Satheesh
I.V. Prakash

Abstract

This paper presents a fully digital, hardware-oriented spiking neural network (SNN) based on Time-to-First-Spike (TTFS) encoding, computing-in-memory-inspired synaptic processing, and Second-Order Leaky Integrate-and-Fire (SOLIF) neurons. Sixteen 4-bit inputs are captured in a shift-register file and converted into temporal spikes by comparing each stored value with a common 4-bit down counter. Binary synaptic weights are represented by a behavioral low-leakage 8T SRAM model, allowing spike-weight multiplication to be implemented using logical AND operations followed by population-count accumulation. Ten parallel SOLIF neurons process the resulting dendrite sums through two leaky integration stages. A Winner-Take-All unit selects the first output neuron that spikes and reports the corresponding class. The modular Verilog architecture reduces multiplier usage, limits spike activity, and supports deterministic timing, making it appropriate for FPGA or ASIC prototyping. The results section is organized for insertion of simulation waveforms, classification outputs, synthesis utilization, timing, and power values

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How to Cite
Chukka, S., D. Satheesh, D. S., & Prakash, I. (2026). Design and Implementation of a Time-to-First-Spike Based Spiking Neural Network Using Digital CIM Architecture and SOLIF Neurons. CINEFORUM, 66(S7), 21–31. https://doi.org/10.66669/cineforum.v66iS7.1684
Issue
Vol. 66 No. S7 (2026)
Section
Original Articles
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This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.

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