Configurable Hierarchical Wafer scale Switch Architecture for Scalable High-Bandwidth Interconnect Systems
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Abstract
This paper provided a hierarchical wafer scale switching architecture which is configurable and scalable and allows communication over a large number of dies at high bandwidth. The structure of the proposed fabric is legislation into the form of Outside, Middle, and Inside Switch Clusters connected with the help of special inter-cluster wiring modules. The architecture, unlike a classic flat two-dimensional mesh, separates the boundary traffic processing, middle redistribution and inner packet forwarding into two layers of communication. Every switch die has three programmable states of the ports unused, packet-switched, and circuit-switched. Packet-switched packet is handled by destination extraction, route-table shared, arbitration and crossbar forwarding, whereas circuit-switched packet take a low-overhead fixed route. Port mode, circuit destination and route-table entries are programmed by a global configuration controller. A shared, dual-table routing structure is used at die level in order to minimize hardware duplication and be available to all active input ports. The RTL-based modular design offers a platform that is sensible to assess hierarchical routing, customizable communication, and a huge scale switchover. A description of the system architecture, packet flow, routing strategy, arbitration mechanism, implementation methodology and evaluation metrics are provided in the paper. The results of simulations are deliberately intended to be inserted only after verification of simulation and synthesis.
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