TriNet-Based Hardware-Aware Deep Learning Framework for Automated Analog Circuit Parameter Prediction
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Abstract
Analog integrated-circuit design is less efficient than virtual design due to the high non-linearity and coupling between performance specifications and device measurements and passive-component values. A hardware-aware TriNet framework is shown in this paper that predicts the parameters of analog circuits directly using design specification. Prediction is done by first normalizing and analyzing the input vector, which includes specifications: gain, bandwidth, phase margin, slew rate, and offset, with a feasibility classifier. Three sequential learners are used to process their valid input: a basic learner refines coarse mapping, an intermediate refiner is used to refine further and an advanced learner can be used to refine even higher order nonlinear correction. Their products are stored and converted back to physical quantities using postprocessing. It is formulated as an architecture and is implemented as fixed-point Verilog and comprises deterministic control, blocking of invalid specifications, and scalable fully connected inference modules. The suggested strategy should decrease the design turnaround time and simulation reliance and maintain physical feasibility. The authors intentionally insert experimental results with data of their synthesis, simulations, forecasts.
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