Optimize Power of CMOS Multiplexer based NOR Gate using Sleepy Stack Technique
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Abstract
In Deep Submicron CMOS digital circuits, analytical analysis of circuit performances, such as the power dissipation and delay, is an important issue. The speed and power consumption trade off against each other. In general, if the speed has top priority, the threshold voltage is reduced and the supply voltage is increased; if the power dissipation has top priority, the threshold voltage is increased and the supply voltage is decreased. In this paper, the analysis of CMOS multiplexer based NOR gate using different technique. To Survey the various existing research works that are relevant to the proposed research work such as sleepy stack, dual stack, zigzag, forced stack etc. To analyze the power gating and multi-threshold CMOS circuits, input vector control and data driven clock circuits that are relevant to the proposed sleepy stack technique. The CMOS circuit is implementing DSCH and draw the layout of MICROWIND software.
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